DDR PCB Design guide

DDR 이 출시된지 오래되었죠?

예전 설계 기억이 나지 않아서 디자인가이드 찾아서 업로드 해봅니다.

이때는 싱글임피던스가 50~60옴 사이라 55옴으로 설계를 많이 했었던 기억이 나네요.

하이스피드 PCB설계가 일반화 되지 않던 때라서 대충? 설계해도 큰 문제는 없었습니다만....

DDR3를 대충? 설계하시는 분들이 꽤 되더라구요~

DDR, DDR2, DDR3, DD4 Topology가 조금 다르니 무시하지 마시길~

데이타 시트의 주요부분입니다.

싱글 : 50~60옴

디퍼런셜 : 100~120옴

Signal length matching is a two-fold item for the board designer. To ensure a robust interface, the designer 

must address both components. First, adhere to the absolute routed maximums to prevent signal integrity 

issues. As the absolute maximums affect component placement, the designer should derive the absolute 

maximums for each signal group before commencing board placement. Absolute maximums are easily 

determined by simulation. In most memory implementations, proper component placement easily satisfies 

the absolute maximums.

Directly or indirectly, all signal groups have some relationship to the clock signal, and the data has an 

additional relationship with its strobe. The second component of length matching deals with the clock-to- 

signal group relationship. This item ensures that sufficient timing margins are available on the interface.

Table 2 illustrates the key length relationships that the board designer should be cognizant of when 

determining the layout rules for the signal groups.