[DDR4] Singal Group, Total Trace Length
Clock CKN[3:0], CKP[3:0] Contol CKE[3:0] Command MA[16:0], BG[1:0], BA[1:0], ACT#, PAR Strobe DQSP[7:0], DQSN[7:0] ECC Strobe DQSP[8], DQSN[8] DATA DQ[63:0] ECC DATA DQ[71:64] Alert ALERT# Reset DRAM_RESET# Rcomp DDR_RCOMP[2:0] Guideline Terminology Descriptions Via Count Motherboard Layer Signal Transition Via Placement Locations. For SO-DIMM designs this identifies the PTH Via Placement Locati..
[ PCB설계실무 ]/DDR4 Design
2019. 8. 16. 21:09
