DDR2 PCB Design Guide Trace length matching

Hardware Tips for Point-to-Point System Design: Termination, Layout, and Routing

 

[Summary]

CK trace length to CK# trace length ±20 mil(0.508mm)

CK/CK# trace lengths to DQS trace length ±500 mil(12.7mm).

CK/CK# trace lengths to address and command groups trace length ±400 mil(40.16mm).

 

Clock Signals

If multiple clock pairs are transmitted from the controller to components, all clock-pair traces should be equivalent within ±20 mil(0.508mm).

 

Matching trace lengths to this level of accuracy helps meet the clock input midpoint voltage (VMP [DC]) data sheet specification.

 

As stated in “Miscellaneous VTT Design Guidelines” on page 6, place a differential termination resistor (RT) of 100–200Ω between CK# and CK near the DDR component input pins.

 

Figures 9 and 10 show recommended DDR routing topology and RT placement for two clock pairs.

• If the trace lengths from split point to DDR components are less than ~1in (2.5cm), use a single 100–120Ω resistor (RT) at the split point (Figure 9).

• If the lengths from the split point to the DRAM devices are greater than ~1in (2.5cm), use two resistors located near the respective DDR components (Figure 10). These resistors are in parallel, so each RT should be 200–240Ω to keep the effective resistance at 100–120Ω.

 

Figure 9: Single CK–CK# Differential Resistor Placement at Split Point

Match clock-pair traces to each signal trace in the address and command groups to within ±400 mil(40.16mm).

If clocks cannot be matched to these groups within 400 mil, then all clock trace lengths must be increased as a group. The longest-to-shortest trace length difference must be ≤800 mil, so both longest and shortest traces determine how much length must be added to all clock lines.

 

SDRAM systems have only a single-ended clock (CLK), so the important trace-matching relationship is not to a second differential clock trace but instead to the other groups. Match clock traces to data group traces within ±500 mil. If multiple clocks are transmitted from the controller to components, all clock-pair traces should be equivalent to within ±20 mil. Matching trace lengths to this level of accuracy helps minimize skew. For both DDR and SDRAM, also match clock traces to each signal trace in the address and command groups to within ±400 mil. If clock traces cannot be matched to the trace lengths of these groups within 400 mil, then all clock trace lengths must be increased as a group. The longest-to-shortest trace-length difference must be ≤800 mil, so both longest and shortest traces determine how much length must be added to all clock lines.

 

Miscellaneous Routing Recommendations

A 400 mil difference in address-, command-, or signal-group trace lengths equates to 0.4in × (1,000ps of propagation delay per 6in of trace), or ~67ps of skew. If the timing budget can absorb this minor amount of lane-to-lane skew and other routing delays, the system will perform normally. Total routing-based delays must meet t DQSCK, controller DQS recovery limits, and other data sheet AC timing parameters. Regardless of bus type, all DDR signal groups must be properly referenced to a solid VSS or VDD plane. For both READs and WRITEs the key relationship is between CK/CK#, DQ, DM, and DQS signals (the DDR data group), which operates at twice the speed of other signal groups, which makes SI more critical. DQ, DQS, and clock lines are best referenced to VSS to minimize noise. If a VSS layer is not easily accessible, address and command lines can reference a VDD layer, though it is generally more noisy. Keep traces as short as possible. If trace length (from controller pad to DRAM pad) is <2in (5cm) for both DDR and SDRAM point-to-point applications, routing simplifies and signal quality usually increases in proportion. In most cases, trace lengths >2in (5cm) lead to more signal undershoot, overshoot, and ringing—all of which are detrimental to SI.

 

Additional Trace-Length Design Guidelines

• Match different DQ byte lanes to within 1in (2.5cm) of each other. A 1in trace-length difference equates to 167ps of propagation delay. Thus, the timing budget must be able to absorb 167ps for a 1in difference in byte-lane matching. – Within a byte lane, match all DQ and DQS traces to within ±50 mil. – Route data groups next to a VSS plane to minimize the return path/loop length. • Maintain a solid ground reference (no splits, etc.) for each group to provide a Low-Z return path; high-speed signals must not cross a plane split.

 

 

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